1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to semiconductor memory devices with a write driver reset circuit.
2. Description of the Background Art
Conventional semiconductor memory devices, dynamic random access memories (DRAMs) in particular, include a DRAM which operates in response to logic combinations of the control signals corresponding to externally applied row address strobe signal/RAS, column address strobe signal/CAS, write enable signal/WE, and output enable signal/OE. The DRAM includes a first-page mode DRAM (FP-DRAM), an extended-output DRAM (EDO-DRAM) and the like as representative examples. The FP-DRAM and the EDO-DRAM operate without receiving an external main clock signal. Such DRAMs recognize control signals/RAS,/CAS,/WE, and /OE input to be logical high when the control signals each have a value no less than an input logical high threshold value determined according to their specifications (referred to as a "VIHmin" hereinafter), and the DRAMs recognize control signals/RAS,/CAS,/WE and/OE to be logical low when the control signals each have a value no more than an input logical low threshold value determined according to their specifications (referred to as a "VILmax" hereinafter). The DRAM have operating states as defined by the logic combinations of the control signals. In addition to the above signals, the DRAM also has an address input (Add), a data input/output (DQ) and the like, and it is so configured that data is read and written from and to a memory cell corresponding to an address. The address signal and the data signal have their respective values VIHmin and VILmax defined as described above.
As an example, FIG. 12 represents a typical read operation of the EDO-DRAM.
At time t1, row address strobe signal/RAS transitions from high to low. Responsively, externally applied address signal Add is taken in and latched as an internal row address signal RA. Then, at time t2, column address strobe signal/CAS transitions from high to low. Responsively, externally applied address signal Add is taken in and latched as an internal column address signal CA. Row and column address signals RA and CA together specify a memory cell. From the memory cell a data signal is read and output as an output data signal Dout via a data input/output (DQ) terminal. Meanwhile, write enable signal AVE has a high level and output enable signal/OE has a low level, since write enable signal/WE having a high level at time t2 is defined to allow the DRAM's operating state to be a read state and output enable signal/OE having a low level is defined to permit a data signal to be output.
As another example, FIG. 13 represents a typical early write operation common to the FP-DRAM and the EDO-DRAM.
FIG. 13 is distinguished from FIG. 12 in that write enable signal/WE has a low level at time t2. As such, an input data signal Din externally received via the data input/output (DQ) terminal is written in a memory cell specified by row and column address signals RA and CA. Furthermore, output enable signal/OE is "Don't Care" and may have a high level or a low level. With write enable signal AVE having a low level at time t2, write operation is performed only once when column address strobe signal/CAS has a low level, and thereafter a read or write operation is never performed again. Because of such definition, write enable signal/WE is "Don't Care" from time t2 onward.
As still another example, FIG. 14 represents a typical delayed write operation common to the FP-DRAM and the EDO-DRAM.
FIG. 14 is distinguished from FIG. 13 in that write enable signal/WE at time t2 is held high, that column address strobe signal/CAS thereafter remains low, and that write enable signal/WE at time t3 transitions from high to low. As such, initially a memory cell specified by both row and column address signals RA and CA taken in at times t1 and t2 is read. It should be noted, however, that for the sake of convenience, output enable signal/OE continues to remain high. As such, in the read operation performed at time t2, data output (DQ) is not permitted, holding a high impedance state HiZ.
Then, with column address strobe signal/CAS remaining low, write enable signal/WE is driven low at time t3. Responsively, input data Din fed via the data input/output (DQ) terminal is taken in and written to a memory cell corresponding to address signals RA and CA having been taken in at times t1 and t2. This address is identical to that of the memory cell having had its data internally read at time t2.
Once a write operation has been performed at time t3, as described above, a read or write operation is never performed again as long as column address strobe signal/CAS remains low, as defined. Thus, write enable signal/WE is "Don't Care" from time t3 onwards.
The FIG. 13 early write operation and the FIG. 14 delayed write operation are summarized as below:
Step 1: when high/RAS and high/CAS transition to low/RAS, the row system is activated;
Step 2: when low/RAS, high/CAS and high/WE transition to low /RAS, low/CAS and low/WE, a write operation is performed; and
Step 3: as long as low/CAS is held, a read or write operation is never performed again.
In step 2, either one of column address strobe signal/CAS and write enable signal/WE may first attain a low level. It should be noted, however, that a write operation is performed when column address strobe signal/CAS and write enable signal/WE are both set low.
To allow a DRAM to operate in such sequence, a column enable signal CE, a write-state signal WS and a write driver enable signal DE are internally generated, as shown in FIG. 15. Column enable signal CE is a signal for activating the column system, write-state signal WS is a signal indicating that the DRAM is placed in the write state, and write driver enable signal DE is a signal for activating a write driver. It should be noted that the figure represents an exemplary delayed write operation.
At time t3, row address strobe signal/RAS, column address strobe signal/CAS and write enable signal/WE are all set low. Thus, write-state signal WS is set high and the DRAM thus enters the write state. If write enable signal/WE is thereafter toggled high and low, write-state signal WS is not reset, since column address strobe signal/CAS is held low. Write-state signal WS is reset when column address strobe signal/CAS returns high, i.e., at time t4, and the DRAM thus exits from the write state.
Write driver enable signal DE goes high in response to write-state signal WE going high, and write driver enable signal DE returns low after a predetermined period of time .tau. elapses.
Since the conventional DRAM responds to activated write enable signal/WE to activate write-state signal WS and also responds to activated write-state signal WS to activate write driver enable signal DE for the predetermined period of time .tau., write enable signal/WE that simply has a narrow noise, as shown in FIG. 16, would disadvantageously activate writes-state signal WS and write driver enable signal DE to cause the DRAM to erroneously perform a write operation.
Such noise of write enable signal/WE is caused by a slight variation in the write enable signal/WE potential that is caused in the system, a slight fluctuation in power supply or ground potential, and the like when the level of write enable signal/WE that is input as for example a high level is close to VIHmin. Since the conventional DRAM is not provided with a means for extending a margin for such noise, write enable signal/WE simply with a short, low-level pulse would set write-state signal WS, and write driver enable signal DE is responsively generated with the same pulse width .tau. as in the normal operation. This can result in an erroneous write operation and thus destroy data.